Realtek PDF datasheets for RTL8309

The RTL8309SB is a 128-pin, ultra low power, high-performance 8-port Fast Ethernet single-chip switch with one extra MII port for specific applications. It integrates all the functions of a high speed switch system—including SRAM for packet buffering, non-blocking switch fabric, address management, one general use MII interface, eight 10/100Base-TX transceivers, and nine Media Access Controllers - into a single 0.18μm CMOS device. It provides compatibility with all industry standard Ethernet and Fast Ethernet devices. Only a 25MHz crystal is required; the EEPROM is optional to save BOM costs.

The embedded packet storage SRAM in the RTL8309SB features superior memory management technology to efficiently utilize the memory space. An integrated 1024-entry look-up table stores MAC address and associated information in a 10-bit direct mapping scheme. The table provides read/write access from the SMI interface, and each of the entries can be configured as a static entry. A static entry indicates that this entry is controlled by the external management processor and automatic aging and learning of the entry will not take place. To prevent MAC address mapping collisions, the embedded 16-entry Content-Addressable Memory (CAM) offers another memory space for recording the MAC address when the mapped entry in the lookup table is occupied. For each incoming packet, the RTL8309SB searches the entries in the lookup table and the 16-entry CAM simultaneously. Then it obtains the correct destination port information to determine which output port the packet should be forwarded to. The aging time of the RTL8309SB is around 300 seconds (this may be sped up to 800μs via EEPROM configuration).

The ninth port of the RTL8309SB implements a MAC module without a PHY transceiver to provide an MII interface for connection with an external PHY or MAC in specific applications. This MII interface may be set to MII PHY mode, SNI PHY mode, or MII MAC mode to work with an external MAC module in a routing engine application, PHY module in a HomePNA application, or other physical layer transceivers. In order to operate correctly, both sides of the connection must be configured to the same speed, duplex, and flow control settings. Four pins are used for the ninth port to force the link status. This interface should be 2.5V or 3.3V compatible depending on the voltage supplied to the power pin VDDIO of this interface.

The RTL8309SB is a 128-pin, ultra low power, high-performance 8-port Fast Ethernet single-chip switch with one extra MII port for specific applications. It integrates all the functions of a high speed switch system—including SRAM for packet buffering, non-blocking switch fabric, address management, one general use MII interface, eight 10/100Base-TX transceivers, and nine Media Access Controllers - into a single 0.18μm CMOS device. It provides compatibility with all industry standard Ethernet and Fast Ethernet devices. Only a 25MHz crystal is required; the EEPROM is optional to save BOM costs.

The embedded packet storage SRAM in the RTL8309SB features superior memory management technology to efficiently utilize the memory space. An integrated 1024-entry look-up table stores MAC address and associated information in a 10-bit direct mapping scheme. The table provides read/write access from the SMI interface, and each of the entries can be configured as a static entry. A static entry indicates that this entry is controlled by the external management processor and automatic aging and learning of the entry will not take place. To prevent MAC address mapping collisions, the embedded 16-entry Content-Addressable Memory (CAM) offers another memory space for recording the MAC address when the mapped entry in the lookup table is occupied. For each incoming packet, the RTL8309SB searches the entries in the lookup table and the 16-entry CAM simultaneously. Then it obtains the correct destination port information to determine which output port the packet should be forwarded to. The aging time of the RTL8309SB is around 300 seconds (this may be sped up to 800μs via EEPROM configuration).

The ninth port of the RTL8309SB implements a MAC module without a PHY transceiver to provide an MII interface for connection with an external PHY or MAC in specific applications. This MII interface may be set to MII PHY mode, SNI PHY mode, or MII MAC mode to work with an external MAC module in a routing engine application, PHY module in a HomePNA application, or other physical layer transceivers. In order to operate correctly, both sides of the connection must be configured to the same speed, duplex, and flow control settings. Four pins are used for the ninth port to force the link status. This interface should be 2.5V or 3.3V compatible depending on the voltage supplied to the power pin VDDIO of this interface.