Realtek device drivers for Windows

Realtek PDF datasheets for RTL8366

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File type


File name rtl8366_rtl8369_datasheet_1.1.pdf
Datasheet version 1.1
Release 2005-09-05  [September '05]
File size 1,46 MB

Realtek PDF datasheet RTL8366 for free download

Designed for the following chipset:
- RTL8366
- RTL8366-GR

The RTL8366 and RTL8369 are 128-pin, ultra-low-power, high-performance 5/8-port Gigabit Ethernet switches, with one extra GMII/MII/RGMII port for specific applications. They integrate all the functions of a high speed switch system; including SRAM for packet buffering, non-blocking switch fabric, and internal register management into a single 0.15µm CMOS device. Only a 25MHz crystal is required; an optional EEPROM is offered for internal register configuration.

The embedded packet storage SRAM in the RTL8366/8369 features superior memory management technology to efficiently utilize memory space. An integrated 4K-entry look-up table stores MAC addresses and associated information in a 12-bit direct mapping scheme. The table provides read/write access from the EEPROM Serial Management Interface (SMI), and each of the entries can be configured as a static entry. The entry aging time is between 200 and 400 seconds.

The RTL8369 implements a 4 channel Reduced Serial Gigabit Media Independent Interface (RSGMII) 2.5GHz serial differential interface that connects with 4 RTL8212’s. Each channel carries 2Gbps of data to and from the RTL8212. The RSGMII interfaces help reduce PCB size and layout complexity.

The 6/9th port of the RTL8366/8369 implements a GMII/MII/RGMII interface for connecting with an external PHY or MAC in specific applications. This interface could be connected to an external CPU or RISC in 1 WAN + 4 LAN or 1 WAN + 8 LAN Router applications. In router applications, the RTL8366/8369 supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on egress. When using this function, VID information carried in the VLAN tag will be changed to PVID.

The RTL8366/8369 supports standard 802.3x flow control frames for full duplex, and optional backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the availability of system resources, including packet buffers and transmitting queues.

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